EECE.5625
The description for this course is not yet available.
EECE.5775
The description for this course is not yet available.
EECE.6515
The description for this course is not yet available.
EECE.5620 VHDL/Verilog Synthesis & Design (3cr)
This course covers digital chip design, synthesis, verification, and test using Hardware Description Languages (HDLs). This class will thoroughly cover important features of the following Hardware Description Languages (HDLs): Verilog, VHDL (VHSIC Hardware Description Language) and System Verilog. These HDLs will be presented with primary emphasis on the synthesizable design aspects of the languages. Therefore, these HDLs will be used for chip design. In addition to using HDLs for digital design, these HDLs will also be used for design verification. Hardware Description Languages (HDLs) will be utilized to design, synthesize and verify digital chip designs. The design and structure of HDL code for effective FPGA and ASIC synthesis will be explored. The design process and verification process for FPGAs and ASICs will be thoroughly reviewed. The Synthesis process for FPGAs and ASICs will thoroughly reviewed, including the following: step by step synthesis process flows, the impact of synthesis constraints, and synthesis scripts for FPGA and ASIC design. Key concepts in functional design verification for ASICs & FPGAs will be explored. Other topics may include the following: High speed digital design, interface to SDRAM devices, embedded processors (hardware, software, test implications), HDL design techniques for effective logic synthesis, chip partitioning, ASIC and FPGA top-down design structure, pipelining, resource/speed trade offs, high speed DSP structures, high speed cache design, resources sharing and design of arbiters. Additional topics to be covered include the following: Design for Test (DFT), Memory Built in Self Test, Logic Built in Self Test, scan chain design, shadow scan design, JTAG, observability bus design, test vector generation & fault coverage.
Requirements:
EECE 2650, EECE 3650 pre-req
EECE.5750 Field Programmable Gate Arrays Logic Design Techniques (3cr)
Advanced logic design techniques using field programmable gate arrays (FPGAs), programmable logic devices, programmable array logic devices, and other forms of reconfigurable logic. Architectural descriptions and design flow will be covered as well as rapid prototyping techniques, ASIC conversions, in-system programmability, high level language design techniques, and case studies highlighting the tradeoffs involved in designing digital systems with programmable devices. This course is generally offered summers only.
EECE.5755 FPGA Logic Design Techniques Lab (1cr)
This lab course is offered to provide the student with the practical skills required to design and implement an FPGA. The student will design commonly used FPGA structures such as state machines and data processing elements and learn how to include library components such as FIFOs, memory interfaces and computer/debug interfaces. The student will work through all phases of development: coding, simulation, building and testing the FPGA on hardware. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.
EECE.5770 Verification of Very Large Digital Designs (3cr)
The increasing complexity of digital designs
coupled with the requirement for first pass
success creates a need for an engineered approach
to verification. This course defines the goals for
verification, presents techniques and
applications, and develops a framework for
managing the verification process from concept to
reality. Course topics include verification tools,
verification languages, verification planning,
stimulus and responses, system Verilog, etc.
Requirements:
EECE.5740 Advanced Logic Design or Equivalent.
EECE.6510 Advanced Embedded System Design with FPGA (3cr)
This course covers the topics related to FPGA based embedded systems, including microprocessor architectures, embedded system architecture, firmware, bootloader, JTAG etc., bare metal processor vs embedded OS, ard core and soft core IP's, interconnects between processor and FPGA, buses and interfaces, and external devices such as sensors and cameras. Labs are included for practice the design of FPGA based embedded systems.
Requirements:
EECE.4820 or EECE.5610 Computer Architecture & Design, and EECE.4800 or EECE.5520 Microprocessor Systems II & Embedded Systems.