VHDL/Verilog Synthesis & Design

Catalog Search > Engineering/Engineering Technology > 16.602

Note: This course is not available for the current semester.

Course No: 16.602; Last Offered: No Data;

Course Description

There will be a series of seminars by distinguished researchers from academia and industry, in addition to UML faculty. Moreover, there will be seminars dedicated to instructional sessions in library services, introduction to Department and Faculty research, and information of thesis requirements and professional ethics. Attendance is mandatory for doctoral and MS students with thesis option. The students are required to write short reports summarizing the talk after each seminar. This course is offered in the spring semester.

Prerequisites & Notes

  • Prerequisites:
  • Special Notes:
  • Credits: 3;

Questions About This Course?

Contact the Advising Center at 978-934-2474 or Continuing_Education@uml.edu

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