Spring 2021
> Engineering/Engineering Technology
> EECE.5620
> 001
Course No: EECE.5620-001; SIS Class Nbr: 3847; SIS Term: 3030
Course Status: Registration Closed
Course Description
Circuit and system representations including behavioral, structural, and physical descriptions using HDL. Modeling of short and narrow MOS transistors for submission applications. Overview of CMOS technology including oxidation, epitaxy, deposition, ion implantation and diffusion essential for multi-layer vias. 2-0 and 4-0 memory structures, I/O structures and PADS. System design including structural, hierarchy, regularity, modularity and programmable gate arrays. RTL synthesis, layout and placement, design capture tools, including schematic, netlist, verification and simulation. Fast adders, sub-tractors, multipliers, dividers, ALUs, CPUs, RAMs, ROMs, row/column decoders, FIFOS, and FSMs with detailed examples. A RISC microcontroller, pipeline architecture including logic blocks, data paths, floor planning, functional verification and testing. Layout and simulation of chips as well as of PCs based on VHDL, verilog, and HILO will be encouraged. A project of industrial vigor for fabrication at MOSIS is required.
Prerequisites, Notes & Instructor
- Prerequisites: EECE 2650 Intro Logic Design and EECE 3650 Electronics I
- Core Codes: STEM
- Credits: 3; Contact Hours: 3
- Instructor: Terence Kelly
-
UMass Lowell Bookstore
When Offered & Tuition
- M | 6:30 PM-9:20 PM EDT
- 2021 Spring: Jan 25 to May 08
- Course Level: Graduate
-
Tuition: $1725
- Note: There is a $30 per semester registration fee for credit courses.
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