Fall 2024
> Engineering/Engineering Technology
> EECE.5520
> 031V
Course No: EECE.5520-031V; SIS Class Nbr: 14261; SIS Term: 3410
Course Status: Registration Closed
Course Description
CPU architecture, memory interfaces and management, coprocessor interfaces, bus concepts, bus arbitration techniques, serial I/O devices, DMA, interrupt control devices. Including Design, construction, and testing of dedicated microprocessor systems (static and real-time). Hardware limitations of the single-chip system. Includes micro-controllers, programming for small systems, interfacing, communications, validating hardware and software, microprogramming of controller chips, design methods and testing of embedded systems.
Prerequisites, Notes & Instructor
- Prerequisites: Students with a CSCE career need permission to take Graduate Level Courses.
- Section Notes: HyFlex Course
- Core Codes: STEM, HYFX
- Credits: 3; Contact Hours: 3
- Instructor: Yan Luo
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Textbook Information
When Offered & Tuition
- W | 6:30 PM-9:20 PM ET Online
- 2024 Fall: Sep 04 to Dec 20
- Course Level: Graduate
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Tuition: $2250
- Note: There is a $30 per semester registration fee for credit courses.
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