VHDL/Verilog Synthesis & Design Lab

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Note: This course is not available for the current semester.

Course No: EECE.5625L; Last Offered: Fall 2020;

Course Description

This lab course is offered to provide the student practical applications of advanced FPGA topics. The lab will focus on advanced language constructs and effective coding for synthesis. Timing closure techniques and synthesis optimization for speed vs power will be explored. Features of synthesis tools including partial reconfiguration, tool reports and clock domain crossing will be evaluated. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.

Prerequisites & Notes

  • Prerequisites:
  • Special Notes:
  • Credits: 1; Contact Hours: 1

Questions About This Course?

Contact the Advising Center at 978-934-2474 or Continuing_Education@uml.edu

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