Computer Architecture and Design

Course Search > Computer Related > EECE.4820

Course No: EECE.4820-021; SIS Class Nbr: 3280; SIS Term: 2840
Course Status: Registration Closed

Course Description

Structure of computers, past and present: first, second, third and fourth generation. Combinatorial and sequential circuits. Programmable logic arrays. Processor design: information formats, instruction formats, arithmetic operations and parallel processing. Hardwired and microprogrammed control units. Virtual, sequential and cache memories. Input-output systems, communication and bus control. Multiple CPU systems.

Prerequisites, Notes & Instructor

  • Prerequisites: EECE 3170 Microprocessor Sys Desgn I,EECE 2650 Intro Logic Design
  • Special Notes:
  • Section Notes:
  • Credits: 3; Contact Hours: 3
  • Instructor: Martin Margala
  • Textbook Information

When Offered & Tuition

  • M,W | 3:30 PM-6:20 PM
  • Summer 2019: Jul 08 to Aug 15
  • Course Level: Undergraduate
  • Tuition: $1020
  • Note: There is a $30 per semester, nonrefundable registration fee for credit courses.

Friday Class Meetings for On Campus / Face-to-Face Courses

Unless otherwise noted above

  • Summer I Mon/Wed Evening Courses: Meet May 20-July 1 and include 3 FRIDAYS: May 24, June 7 and June 21 at the regularly scheduled hours.
  • Summer I Tues/Thurs Evening Courses: Meet May 21-July 1 include 2 FRIDAYS: May 31 and June 14 at the regularly scheduled hours.
  • Summer II Mon/Wed Evening Courses: Meet July 8 to Aug 15 include 2 FRIDAYS: July 12, July 26 at the regularly scheduled hours.
  • Summer II Tues/Thurs Evening Courses: Meet July 9 to Aug 15 include 2 FRIDAYS: July 19 and August 12 at the regularly scheduled hours.

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