× DISMISS Reminder: if you are taking an on campus or hybrid course, classes during the week of Jan. 25 - Jan 30 will be held remotely.

VHDL/Verilog Synthesis & Design Lab

Course Search > Engineering/Engineering Technology > EECE.5625L

Course No: EECE.5625L-041; SIS Class Nbr: 16189; SIS Term: 3010
Course Status: Open Added 8/14/20

Course Description

This lab course is offered to provide the student practical applications of advanced FPGA topics. The lab will focus on advanced language constructs and effective coding for synthesis. Timing closure techniques and synthesis optimization for speed vs power will be explored. Features of synthesis tools including partial reconfiguration, tool reports and clock domain crossing will be evaluated. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.

Prerequisites, Notes & Instructor

When Offered & Tuition

  • TBD
  • Fall 2020: Sep 01 to Dec 18
  • Course Level: Graduate
  • Tuition: $575
  • Note: There is a $30 per semester registration fee for credit courses.

Every effort has been made to ensure the accuracy of the information presented in this catalog. However, the Division of Graduate, Online & Professional Studies reserves the right to implement new rules and regulations and to make changes of any nature to its program, calendar, procedures, standards, degree requirements, academic schedules (including, without limitations, changes in course content and class schedules), locations, tuition and fees. Whenever possible, appropriate notice of such changes will be given before they become effective.

Register for this Course

New Students

If you have not already applied and been accepted to a program.
Register Online

Current Students

If you have applied, been accepted to and are currently enrolled in a program.
Register Now

Additional Registration Information


Email our Advising Center for assistance or call 800-480-3190.