VHDL/Verilog Synthesis & Design Lab

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Course No: EECE.5625L-041; SIS Class Nbr: 16189; SIS Term: 3010
Course Status: Registration Closed

Course Description

This lab course is offered to provide the student practical applications of advanced FPGA topics. The lab will focus on advanced language constructs and effective coding for synthesis. Timing closure techniques and synthesis optimization for speed vs power will be explored. Features of synthesis tools including partial reconfiguration, tool reports and clock domain crossing will be evaluated. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.

Prerequisites, Notes & Instructor

When Offered & Tuition

  • TBD
  • Fall 2020: Sep 01 to Dec 18
  • Course Level: Graduate
  • Tuition: $575
  • Note: There is a $30 per semester registration fee for credit courses.

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Course Registration Closed

The registration period for this course has ended.

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