Field Programmable Gate Arrays Logic Design Techniques

Course Search > Engineering/Engineering Technology > EECE.5750

Course No: EECE.5750-011; SIS Class Nbr: 1085; SIS Term: 2940
Course Status: Open

Course Description

Advanced logic design techniques using field programmable gate arrays (FPGAs), programmable logic devices, programmable array logic devices, and other forms of reconfigurable logic. Architectural descriptions and design flow will be covered as well as rapid prototyping techniques, ASIC conversions, in-system programmability, high level language design techniques, and case studies highlighting the tradeoffs involved in designing digital systems with programmable devices. This course is generally offered summers only.

Prerequisites, Notes & Instructor

  • Prerequisites: Students with a CSCE career need permission to take Graduate Level Courses.
  • Special Notes:
  • Section Notes: Virtual Classroom Course
  • Core Codes: STEM, VRCL
  • Credits: 3; Contact Hours: 3
  • Instructor: Jim Moran
  • Textbook Information

When Offered & Tuition

  • T,Th | 6:00 PM-8:50 PM EDT
  • Summer 2020: May 18 to Jun 29
  • Course Level: Graduate
  • Tuition: $1725
  • Note: There is a $30 per semester registration fee for credit courses.

Friday Class Meetings for Virtual Courses

Unless otherwise noted above

  • Summer Start I M/W classes begin on Monday May 18 and include 3 FRIDAYS: May 22, June 5 and June 19 at the regularly scheduled hours.
  • Summer Start I T/Th classes begin on Tuesday, May 19 and include 2 FRIDAYS: May 29 and June 12 at the regularly scheduled hours.
  • Summer Start II M/W classes begin on Monday, July 6 and include 2 FRIDAYS: July 10 and July 24 at the regularly scheduled hours.
  • Summer Start II T/Th classes begin on Tuesday, July 7 and include 2 FRIDAYS: July 17 and July 31 at the regularly scheduled hours.

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