Course No: EECE.5775L-041; SIS Class Nbr: 14249; SIS Term: 3030
Course Status: Open Added 11/4/20
This lab course is offered to provide the student with the practical skills to verify an FPGA design in simulation environment. The student will build various components of a test environment beginning with a basic testbench using manual verification and progressing to a more robust self-checking test environment. This includes generating constrained random stimulus and predicting, monitoring, and checking responses. The students will also create a regression test suite and evaluate coverage. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.
Every effort has been made to ensure the accuracy of the information presented in this catalog. However, the Division of Graduate, Online & Professional Studies reserves the right to implement new rules and regulations and to make changes of any nature to its program, calendar, procedures, standards, degree requirements, academic schedules (including, without limitations, changes in course content and class schedules), locations, tuition and fees. Whenever possible, appropriate notice of such changes will be given before they become effective.
Additional Registration Information